module lab2 (
    input clk,
    input rst,
    input [3:0] key_row,
    output reg [3:0] key_col,
    output reg [7:0] seg
);

  reg [1:0] cnt;

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      cnt <= 1'b0;
    end else begin
      cnt <= cnt + 1'b1;
    end
  end

  always @(*) begin
    case (cnt)
      2'b00:   key_col = 4'b0111;
      2'b01:   key_col = 4'b1011;
      2'b10:   key_col = 4'b1101;
      2'b11:   key_col = 4'b1110;
      default: key_col = 4'b1111;
    endcase
  end

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      seg <= 8'b00000000;
    end else begin
      case ({
        key_col, key_row
      })
        8'b0111_0111: seg <= 8'b00000110;  //"1"
        8'b0111_1011: seg <= 8'b01011011;  //"2"
        8'b0111_1101: seg <= 8'b01001111;  //"3"
        8'b0111_1110: seg <= 8'b01110111;  //"A"

        8'b1011_0111: seg <= 8'b01100110;  //"4"
        8'b1011_1011: seg <= 8'b01101101;  //"5"
        8'b1011_1101: seg <= 8'b01111101;  //"6"
        8'b1011_1110: seg <= 8'b01111100;  //"b"

        8'b1101_0111: seg <= 8'b00000111;  //"7"
        8'b1101_1011: seg <= 8'b01111111;  //"8"
        8'b1101_1101: seg <= 8'b01101111;  //"9"
        8'b1101_1110: seg <= 8'b00111001;  //"c"

        8'b1110_0111: seg <= 8'b01111001;  //"E"
        8'b1110_1011: seg <= 8'b00111111;  //"0"
        8'b1110_1101: seg <= 8'b01110001;  //"F"
        8'b1110_1110: seg <= 8'b01011110;  //"d"

        default: seg <= seg;
      endcase
    end
  end

endmodule
